Highly integrated semiconductor devices having rapid data transfer rates are in demand. However, certain characteristics of a semiconductor device may degrade as the semiconductor device becomes more highly integrated. For example, the width of transistor gate electrodes and impurity regions such as transistor source and drain regions are typically made smaller as the level of integration is increased. Such reductions in the line width of gate electrodes and impurity regions may degrade various characteristics of a transistor through an effect that is widely known as a short channel effect.
When a conventional polysilicon layer is formed on a contact area of a highly integrated semiconductor device, the contact resistance or sheet resistance may become very high, which can result in increased power consumption and/or decreased device operating speed. Consequently, a metal silicide layer is often formed on the gate electrode and source/drain regions to facilitate reducing the contact resistance or the sheet resistance, thereby improving the conductivity of the contact in the semiconductor device.
To form such a metal silicide layer, a metal such as, for example, titanium (Ti), nickel (Ni) or cobalt (Co), is deposited on an underlying layer that includes silicon, to form a metal layer on the underlying layer. The device is then heated, and silicon (Si) in the underlying layer reacts with metal in the metal layer to form a metal silicide layer on the underlying layer such as a titanium silicide, a nickel silicide or a cobalt silicide layer. Cobalt silicide layers are widely used because cobalt silicide may be less influenced by a critical dimension (CD) of a gate electrode of the semiconductor device having a design rule of about 200 nm.
To form a cobalt silicide layer for the semiconductor device having a design rule of about 200 nm, cobalt is deposited on a silicon substrate or a silicon pattern by, for example, a chemical vapor deposition (CVD) process to form a cobalt layer on the silicon substrate or pattern. A heat treatment is performed on the cobalt layer, and the cobalt and the silicon react with each other to form the cobalt silicide layer on the silicon substrate or the silicon pattern.
However, when the design rule for the semiconductor device is reduced below about 100 nm, it may become more difficult to provide a relatively high quality cobalt silicide layer. For example, the cobalt silicide may partially agglomerate in some areas, and may fail to form in other areas, resulting in a cobalt silicide layer that may include broken areas and/or be formed discontinuously along the gate electrode and source/drain regions due to a non-uniform distribution of the cobalt silicide. The agglomeration and discontinuities in the cobalt silicide layer may be caused by intrinsic properties of metal silicide.
Examples of methods of forming transistors including metal silicide layers are disclosed in Japanese Patent Laid-Open Publication No. 1988-233371 and U.S. Pat. No. 5,646,070.
FIG. 1 is a flowchart illustrating a conventional method for forming a metal silicide layer.
Referring to FIG. 1, a gate electrode and source/drain regions for a transistor are formed on a substrate (step S10). Then, a cobalt layer and an anti-oxidation layer such as a titanium nitride (TiN) layer are sequentially formed on the gate electrode and the source/drain regions (step S20). A first heat treatment is performed on the cobalt layer and the anti-oxidation layer to form a preliminary cobalt silicide (CoSi) layer on the source/drain regions and on the gate electrode by a chemical reaction of cobalt (Co) and silicon (Si) (step S30). The anti-oxidation layer and residual cobalt (Co) that did not react with the silicon (Si) are removed from the substrate, thereby exposing the preliminary cobalt silicide layer (step S40). A tungsten layer is formed on the preliminary cobalt silicide layer (step S50), and a second heat treatment is performed on the tungsten layer, thereby transforming the preliminary cobalt silicide layer into a cobalt silicide layer that has a very stable electrical resistance (step S60). Then, an insulation interlayer is formed on the resultant structure.